Basics of computer architecture 

                                                            Introduction

1.1    Computer Organization and Architecture

•   Computer Architecture refers to those elements/property  of a system that have a direct effect  on the logical execution/ implementation of a program.

•  the number of bits used to represent various data types 
•  I/O mechanisms 
•  memory addressing techniques

In, other words it can be defined as,

the study of internal working , structuring and implementation of computer system.

Computer Organization concerned with the structure and behavoiur of computer system as seen by the user.  

• Example: hardware details transparent to the programmer, such as control signals, interfaces between the computer and memory technology used.

Components of computer organization:

input unit, output unit, storage unit, arithmetic logic unit , control unit etc.

• Examples are things that are transparent to the programmer:

• control signals 
• interfaces between computer and peripherals 
• the memory technology being used

• Architecture is those attributes visible to the programmer o Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques.

• Organization is how features are implemented  Control signals, interfaces, memory technology.

i.e, the knowing , what the functional components of computer are, how they work and how their performance is measured and optimized. 

• All Intel x86 family share the same basic architecture 

• The IBM System/370 family share the same basic architecture

• This gives code similarity 

     At least backwards

• Organization differs between different versions

1.2 Structure and Function

                           Fig: Functional view of a computer

                        Fig: Processing from / to storage

                            Fig: Processing from storage to i/o

      Main components of CPU:

1. Central processing unit

2. Main memory

3.I/O

4. System interconnections

CPU main components:

1.   Control unit 
   
2. Arithemetic and logic unit(ALU) 
3.  Registers 
4.  CPU interconnections 

 

Fig: Computer: Top level structure 

                                  Fig. central processing unit 

1.3 Designing for performance 

Some of the driving cause behind the need to design for performance:

• Microprocessor Speed 
• Pipelining 
•  Branch prediction: The processor looks ahead in the instruction code get from memory and see which branches, or group of instructions are  to be processed next. 

•  Data flow analysis: The processor analyzes which instructions are dependent on each other’s results, or data, to create a schedule of instructions to prevent delay.

•  Speculative execution: an optimization in which CPU performs a series of tasks before it is prompted to, in order to have information ready if it is required at any point. 

 

 • Performance Mismatch 

1.  Processor speed increased 
2. Memory capacity increased 
3. Memory speed lags behind 

depicts the history; while processor speed and memory capacity have grown rapidly, the speed with which data can be transferred between main memory and the processor has lagged badly.

     Fig: Evolution of DRAM and processor 8

The amount of main memory needed is going up, but DRAM density is going up faster (number of DRAM per system is going down).

 

Fig: Trends in DRAM use

Solutions:

•  Increase number of bits retrieved at one time 

1.  Make DRAM “wider” rather than “deeper” to use wide bus data paths

•  Change DRAM interface 

1.  Cache

•  Reduce frequency of memory access 
•  More complex cache and cache on chip 
•  Increase interconnection bandwidth 

1.  High speed buses 
2.  Hierarchy of buses

1.4 Computer Components:

• The Control Unit (CU) and the Arithmetic and Logic Unit (ALU) constitute the Central Processing Unit (CPU) 

• Data and instructions need to get into the system and results need to get out 

1.  Input/output (I/O module) 

• Temporary storage of code and results is needed 

1.  Main memory (RAM) 

• Program Concept 

1.  Hardwired systems are inflexible 
2.  General purpose hardware can do different tasks, given correct control signals 
3.  Instead of re-wiring, supply a new set of control signals

                  Fig: Hardware and Software Approaches 

1.5 Computer Function 

The basic function performed by a computer is execution of a program, which consists of a set of instructions stored in memory. 

• Two steps of Instructions Cycle: 

1. Fetch 
2. Execute

                             Fig: Basic Instruction Cycle

• Fetch Cycle

•  Program Counter (PC) holds address of next instruction to fetch
•  Processor fetches instruction from memory location pointed to by PC
•  Increment PC 

1. Unless told otherwise

•  Instruction loaded into Instruction Register (IR) 

• Execute Cycle 

•  Processor interprets instruction and performs required actions, such as:

•  Processor - memory 

1.  data transfer between CPU and main memory
2.  Processor - I/O 

•  Data transfer between CPU and I/O module 
• Data processing 

1.  Some arithmetic or logical operation on data

•  Control 

1.  Alteration of sequence of operations 
2.  e.g. jump

•  Combination of above

Fig: Example of program execution 

(consists of memory and registers in hexadecimal)

• The PC contains 300, the address of the first instruction.

 The instruction (the value 1940 in hex) is loaded into IR and PC is incremented. This process involves the use of MAR and MBR.

 • The first hexadecimal digit in IR indicates that the AC is to be loaded. The remaining three hexadecimal digits specify the address (940) from which data are to be loaded. 

• The next instruction (5941) is fetched from location 301 and PC is incremented. 

• The old contents of AC and the contents of location 941 are added and the result is stored in the AC.

 • The next instruction (2941) is fetched from location 302 and the PC is incremented. 

9

• The contents of the AC are stored in location 941. 

Interrupts: 

• Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing.

• Program o e.g. overflow, division by zero.

 • Timer o Generated by internal processor timer o Used in pre-emptive multi-tasking.

 • I/O o from I/O controller.

 • Hardware failure 

 e.g. memory parity error 

•  Indicated by an interrupt signal

1.   If no interrupt, fetch next instruction
2.   If interrupt pending: 

•  Suspend execution of current program
•  Save context 
• Set PC to start address of interrupt handler routine 
•  Process interrupt 
•  Restore context and continue interrupted program

                    Fig: Transfer of control via interrupts

              Fig: Instruction cycle state diagram, with interrupts

• Multiple Interrupts 

-Disable interrupts (approach #1) 

•  Processor will ignore further interrupts whilst processing one interrupt
•  Interrupts remain pending and are checked after first interrupt has been processed
•  Interrupts handled in sequence as they occur 

- Define priorities (approach #2) 

• Low priority interrupts can be interrupted by higher priority interrupts 
•  When higher priority interrupt has been processed, processor returns to previous interrupt.

1.6 Interconnection structures:

The collection of paths connecting the various modules is called the interconnecting structure.

 • All the units must be connected 

• Different type of connection for different type of unit 

1.  Memory
2.  Input/Output
3.  CPU

•  Memory Connection 

1.  Receives and sends data 
2.  Receives addresses (of locations) 
3.  Receives control signals 

i) Read 

ii)Write

iii) Timing

• I/O Connection 

1.  Similar to memory from computer’s viewpoint 
2. Output 

•  Receive data from computer
•  Send data to peripheral 

1. Input 

•  Receive data from peripheral
•  Send data to computer 

1.  Receive control signals from computer 
2. Send control signals to peripherals 

• e.g. spin disk o Receive addresses from computer 
• e.g. port number to identify peripheral 

1.  Send interrupt signals (control)

1.7 Bus interconnection:

• A bus is a communication pathway connecting two or more devices

 • Usually broadcast (all components see signal) 

• Often grouped 

1. A number of channels in one bus 
2.  e.g. 32 bit data bus is 32 separate single bit channels

 • Power lines may not be shown 

• There are a number of possible interconnection systems 

• Single and multiple BUS structures are most common • e.g. Control/Address/Data bus (PC) 

 e.g. Unibus (DEC-PDP) 

• Lots of devices on one bus leads to:

1.   Propagation delays
2.  Long data paths mean that co-ordination of bus use can adversely affect performance
3.  If aggregate data transfer approaches bus capacity

 • Most systems use multiple buses to overcome these problems

Fig: Bus Interconnection Scheme